1. Field of the Invention
This invention relates to a method for fabricating multilevel interconnects, and more particularly, to a method for manufacturing a dual damascene structure.
2. Description of Related Art
As the initegration of a semiconductor device is increased, the resistance-capacitance dela resulting from the parasitic capacitance generated by an inter-metal dielectric layer is worsened. Hence, it is common to utilize a low-permittivity dielectric to form an inter-metal dielectric in a sub-micron semiconductor. In the damascene process, the low-permittivity dielectric layer is usually used to reduce interconnection parasitic capacitance, hence the operation speed is improved. Therefore, the low-permittivity dielectric layer is a very popular IMD material for use in high-speed integrated circuits (IC).
A dual damascene process is a technique which imbeds metal plugs into an insulator and forms an aluminum metal layer on the substrate to connect the metal plugs. The dual damascene process is a process for manufacturing metal lines with high reliability and low cost. Materials used in the interconnections are not limited by the etching process of the metal. As a result, the dual damascene structure has been widely used in the manufacturing process for copper conductive lines so that the resistance of the conductive line is reduced for increasing the operation speed and quality of the integrated circuit. As the integration of a semiconductor device is increased, the dual damascene structure using dielectric layers with low-permittivity is used more in the semiconductor processes for manufacturing metal interconnections.
FIGS. 1A through 1D are schematic, cross-sectional views showing a conventional method for fabricating a dual damascene structure.
Referring to FIG. 1A, a substrate 100 contains a metal layer 102 is provided. A dielectric layer 104, an etching stop layer 106 and a dielectric layer 108 are formed on a provided substrate 100, in sequence. A photoresist layer 110 is then formed on the dielectric layer 108. A conventional photolithography method is applied to pattern the photoresist layer 110 so as to form the pattern for a via opening.
Referring to FIG. 1B, the dielectric layer 108 etching stop layer 106 and dielectric layer 104 are etched to form the via opening 112 exposing the metal layer 102, with the patterned photoresist layer 110 serving as a mask. The photoresist layer 110 is then removed followed by the step of forming another photoresist layer 114 on the substrate 100. A conventional photolithography method is applied to pattern the photoresist layer 110, so as to form a trench pattern.
Referring to FIG. 1C. the dielectric layer 108 is then etched to form the trench 116, with the photoresist layer 108 and etching stop layer 108 serving as a mask and etching stop point, respectively. Thereafter, the photoresist layer 114 is removed. The trench 116 and via opening 112 are then filled with a metal layer 118 so that a dual damascene structure is formed, as shown in FIG. 1D.
As the integration of a semiconductor device is increased, the resistance-ecapacitance delay resulting from the parasitic capacitance generated by an inter-metal dielectric layer is worsened. Hence, it is common to utilize a low-permittivity dielectric to form an inter-metal dielectric in a sub-micron semiconductor fabrication process for reducing the Resistance-Capacitance Time Delay effect. Conventionally, the photoresist layer is composed of polymer materials and the low-permittivity dielectric also includes organic materials. However, the regions 120 of the dielectric layers 108 and 104 exposed in the via opening 112 may be damaged by the developer during the developing process of the photoresist layers 110 and 114. Therefore, the profile of the dual damascene is destroyed.